A 0.08P2-Sized 8F2 Stack Dram Cell For Multi-Gigabit Dram
...Kim, Woncheol Cho, Min Huh, Gucheol Jeong,
Jaebuhm Suh, Hoyeop Kweon, Jaesung Roh, Kisoo Shin, and Sangdon Lee
Device BT Team, Memory R&D Division, Hynix Semiconductor Co. LTD, San 136-1, Ami-Ri,
Bubal-Eun Ichon-Si. Kvungki-Do. 467-70 1 Korea
Abstract
The first 8F2 Stack DRAM cell with 0.08pm’ size has
been successfully integrated employing poly plug scheme
for landing plug contacts and W/poly gates and Ru MIM
capacitors, of which cell working has been proven under
easy function check mode. Cell transistor with W gate
technology exhibits a sufficient saturation current(bP) of
-40~1A with threshold voltage (Vbat) of 0.9V and
satisfactory ring oscillator delay characteristics of - 5Ops.
INTRODUCTION
The first principle in DRAM integration would be
miniaturization of cell in the viewpoint of cost reduction. In
this study, we have integrated 0.08pm2-sized 8F2 stack
DRAM cell. It is believed that this cell is smallest 8F2 cell
that has been integrated ever. We have employed ArF
patteming to get 100nm-cell resolution. Automatic OPC
and manual OPC is applied to get expected CD for
corelperi Tr with 0.17,m MFS. Noble exposure techaique
of cross-pole illumination with PSM technique was adopted
to enhance the exposure margin. As capacitor technology,
Ru MIM concave capacitor technology was adopted. Key
technology features compared to pervious work are listed
in table 1 [ 11 : STI isolation, WPoly gate, poly-Si or Epi-Si
plug cell contacts, ED 1 BPSG gapfiller, ED2 HDP oxide
gapfiller, line-type SAC Storage node contacts, Ru MIM
capacitor, DLM metallization and ArF patterning
technique[2,3]. Introduction of new technology in
patterning and capacitor technology is ascribed to
integration work below lOOnm regime. Resolution limit of
KrF lithography is expected to be around IlOnm, which
means that sub lOOnm node needs new lithography...
View Full Essay
